roysuparna
Education
Post graduate diploma in VLSI
2019
CDAC ACTS PUNE
Modules completed under this course : Advanced Digital Design Verilog System Verilog UVM System architecture CMOS And Asics Programming Fundamentals Linux and Shell scripting
Bachelor Of Engineering
2018
JORHAT INSTITUTE OF SCIENCE & TECHNOLOGY
Graduated in Electronics & telecommunication with 74.5%
